双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74HCT163D-Q100

Presettable synchronous 4-bit binary counter; synchronous reset

The 74HC163-Q100; 74HCT163-Q100 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula:

fmax = 1 / tP(max)(CP to TC) + tSU(CEP to CP)

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

此产品已停产

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C

  • Complies with JEDEC standard no. 7A

  • Input levels:

    • For 74HC163-Q100: CMOS level

    • For 74HCT163-Q100: TTL level

  • Synchronous counting and loading

  • 2 count enable inputs for n-bit cascading

  • Synchronous reset

  • Positive-edge triggered clock

  • ESD protection:

    • MIL-STD-883, method 3015 exceeds 2000 V

    • HBM JESD22-A114F exceeds 2000 V

    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

  • Multiple package options

Applications

参数类型

型号 Product status VCC (V) Output drive capability (mA) Logic switching levels tpd (ns) fmax (MHz) Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74HCT163D-Q100 End of life 4.5 - 5.5 ± 4 TTL 20 45 low -40~125 83 5.2 41 SO16

封装

下表中的所有产品型号均已停产 。

型号 可订购的器件编号,(订购码(12NC)) 状态 标示 封装 外形图 回流焊/波峰焊 包装
74HCT163D-Q100 74HCT163D-Q100J
(935302102118)
Obsolete no package information

环境信息

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74HCT163D-Q100 74HCT163D-Q100J 74HCT163D-Q100 rohs rhf rhf
品质及可靠性免责声明

文档 (4)

文件名称 标题 类型 日期
74HC_HCT163_Q100 Presettable synchronous 4-bit binary counter; synchronous reset Data sheet 2018-10-12
AN11044 Pin FMEA 74HC/74HCT family Application note 2019-01-09
hc HC/HCT Spice model SPICE model 2022-02-17
HCT_USER_GUIDE HC/T User Guide User manual 1997-10-31

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模型

文件名称 标题 类型 日期
hc HC/HCT Spice model SPICE model 2022-02-17

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.