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74LVC1G175-Q100

Single D-type flip-flop with reset; positive-edge trigger

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • High noise immunity

  • Overvoltage tolerant inputs to 5.5 V

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G175GV-Q100Production1.65 - 5.5CMOS/LVTTL± 323.1300low-40~12523240.0146TSOP6
74LVC1G175GW-Q100Production1.65 - 5.5CMOS/LVTTL± 323.1300low-40~12526539.1154TSSOP6

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC1G175GV-Q100
TSOP6
(SOT457) 		SOT457REFLOW_BG-BD-1
WAVE_BG-BD-1
SOT457_125ActiveV7574LVC1G175GV-Q100H
( 9353 015 06125 )
74LVC1G175GW-Q100
TSSOP6
(SOT363-2) 		SOT363-2SOT363-2_125ActiveYT74LVC1G175GW-Q100H
( 9353 015 07125 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC1G175GV-Q10074LVC1G175GV-Q100H74LVC1G175GV-Q100Always Pb-free
74LVC1G175GW-Q10074LVC1G175GW-Q100H74LVC1G175GW-Q100Always Pb-free
品质及可靠性免责声明

文档 (10)

文件名称标题类型日期
74LVC1G175_Q100Single D-type flip-flop with reset; positive-edge triggerData sheet2023-08-15
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc1g17574LVC1G175 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT363-2plastic thin shrink small outline package; 6 leads; body width 1.25 mmPackage information2022-11-21
MAR_SOT457MAR_SOT457 TopmarkTop marking2013-06-03
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08
SOT457plastic, surface-mounted package (SC-74; TSOP6); 6 leadsPackage information2023-03-03
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06

支持

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模型

文件名称标题类型日期
lvc1g17574LVC1G175 IBIS modelIBIS model2014-10-20

订购、定价与供货

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