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74LVC2G74

Single D-type flip-flop with set and reset; positive edge trigger

The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V)

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G74DCProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12520636.4117VSSOP8
74LVC2G74DPProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12522021.3107TSSOP8
74LVC2G74GNProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12524712.1155XSON8
74LVC2G74GSProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12528412.3152XSON8
74LVC2G74GTProduction1.65 - 5.5CMOS/LVTTL± 323.5280low-40~1253396.8166XSON8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC2G74DC
VSSOP8
(SOT765-1) 		SOT765-1SOT765-1_125ActiveV7474LVC2G74DC,125
( 9352 803 91125 )
74LVC2G74DP
TSSOP8
(SOT505-2) 		SOT505-2SOT505-2_125ActiveV7474LVC2G74DP,125
( 9352 803 88125 )
74LVC2G74GN
XSON8
(SOT1116) 		SOT1116REFLOW_BG-BD-1
SOT1116_115ActiveY474LVC2G74GN,115
( 9352 922 48115 )
74LVC2G74GS
XSON8
(SOT1203) 		SOT1203REFLOW_BG-BD-1
SOT1203_115ActiveY474LVC2G74GS,115
( 9352 927 99115 )
74LVC2G74GT
XSON8
(SOT833-1) 		SOT833-1SOT833-1_115ActiveV7474LVC2G74GT,115
( 9352 803 89115 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC2G74DC74LVC2G74DC,12574LVC2G74DCAlways Pb-free
74LVC2G74DP74LVC2G74DP,12574LVC2G74DPAlways Pb-free
74LVC2G74GN74LVC2G74GN,11574LVC2G74GNAlways Pb-free
74LVC2G74GS74LVC2G74GS,11574LVC2G74GSAlways Pb-free
74LVC2G74GT74LVC2G74GT,11574LVC2G74GTAlways Pb-free
品质及可靠性免责声明

文档 (15)

文件名称标题类型日期
74LVC2G74Single D-type flip-flop with set and reset; positive edge triggerData sheet2023-08-22
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc2g7474LVC2G74 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2022-06-03
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2022-06-03
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2022-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2022-06-02
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06

支持

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模型

文件名称标题类型日期
lvc2g7474LVC2G74 IBIS modelIBIS model2014-10-20

订购、定价与供货

样品

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