74AVCH16T245

16-bit dual supply translating transceiver with configurable voltage translation; 3-state

The 74AVCH16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs. The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (V_CC(A) and V_CC(B)) for voltage translation and four 8-bit input-output ports (nAn, nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. V_CC(A) and V_CC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state

The device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND level, both A and B outputs are in the high-impedance OFF-state. The bus-hold circuitry on the powered-up side always stays active.

The 74AVCH16T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

特性

Wide supply voltage range: V_CC(A): 0.8 V to 3.6 V and V_CC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3B exceeds 8000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101D exceeds 1000 V
Maximum data rates:
- 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
- 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
- 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
- 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I_OFF circuitry provides partial Power-down mode operation
Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type number	Product status	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AVCH16T245DGG	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	2.1	16	very low	-40~125	81	1.7	34	TSSOP48

封装

型号	封装	尺寸版本	回流焊/波峰焊	包装	状态	标示	可订购的器件编号，（订购码(12NC)）
74AVCH16T245DGG	TSSOP48 (SOT362-1)	SOT362-1	SSOP-TSSOP-VSO-WAVE	SOT362-1_118	Active	AVCH16T245	74AVCH16T245DGG,18 ( 9352 862 33118 )

停产信息

型号	可订购的器件编号，（订购码(12NC)）	最后一次购买日期	最后一次交货日期	替代产品
74AVCH16T245DGG	935286233518
74AVCH16T245DGG	935286233512
74AVCH16T245DGG	935286233112	2021-06-30	2021-12-31	74AVCH16T245DGG

环境信息

型号	可订购的器件编号	化学成分	RoHS	RHF指示符	无铅转换日期
74AVCH16T245DGG	74AVCH16T245DGG,18	74AVCH16T245DGG			Always Pb-free

品质及可靠性免责声明

文档 (6)

文件名称	标题	类型	日期
74AVCH16T245	16-bit dual supply translating transceiver with configurable voltage translation; 3-state	Data sheet	2019-04-03
Nexperia_document_guide_Logic_translators	Nexperia Logic Translators	Brochure	2021-04-12
avch16t245	74AVCH16T245 Ibis model	IBIS model	2014-10-14
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08
SOT362-1	plastic thin shrink small outline package; 48 leads; body width 6.1 mm	Package information	2024-01-05

支持

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模型

文件名称	标题	类型	日期
avch16t245	74AVCH16T245 Ibis model	IBIS model	2014-10-14

订购、定价与供货

74AVCH16T245DGG

样品

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