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74AXP8T245

8-bit dual supply translating transceiver; 3-state

The 74AXP8T245 is an 8-bit dual supply translating transceiver with 3-state outputs that enable bidirectional level translation. It features two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is required and output glitches during power supply transitions are prevented using patented circuitry. As a result glitches will not appear on the outputs for supply transitions during power-up/down between 20 mV/µs and 5.5 V/s.

Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

特性

  • Wide supply voltage range:

    • VCC(A): 0.9 V to 5.5 V

    • VCC(B): 0.9 V to 5.5 V

  • Low input capacitance; CI = 1.5 pF (typical)

  • Low output capacitance; CO = 3.8 pF (typical)

  • Low dynamic power consumption; CPD = 10 pF (typical)

  • Low static power consumption; ICC = 2 μA (25 °C maximum)

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-12 (1.1 V to 1.3 V; inputs)

    • JESD8-11 (1.4 V to 1.6 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD12-6 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Latch-up performance exceeds 100 mA per JESD78D Class II

  • Inputs accept voltages up to 5.5 V

  • Low noise overshoot and undershoot < 10% of VCCO

  • IOFF circuitry provides partial power-down mode operation

  • Specified from -40 °C to +125 °C

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AXP8T245BQProduction0.9 - 5.50.9 - 5.5CMOS± 1294ultra low-40~125686.442DHVQFN24
74AXP8T245PWProduction0.9 - 5.50.9 - 5.5CMOS± 1294ultra low-40~125812.337TSSOP24

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AXP8T245BQ
DHVQFN24
(SOT815-1) 		SOT815-1SOT815-1_118ActiveAXP8T24574AXP8T245BQJ
( 9356 908 13118 )
74AXP8T245PW
TSSOP24
(SOT355-1) 		SOT355-1SSOP-TSSOP-VSO-WAVE
SOT355-1_118Active4AXP8T24574AXP8T245PWJ
( 9356 908 12118 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AXP8T245BQ74AXP8T245BQJ74AXP8T245BQweek 25, 2019
74AXP8T245PW74AXP8T245PWJ74AXP8T245PWweek 25, 2019
品质及可靠性免责声明

文档 (7)

文件名称标题类型日期
74AXP8T2458-bit dual supply translating transceiver; 3-stateData sheet2020-02-11
AN90029Pin FMEA for AXPnT familyApplication note2021-07-13
axp8t24574AXP8T245 IBIS modelIBIS model2020-11-20
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904AXP – Extremely low-power logic technology portfolioLeaflet2019-04-05
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT355-1plastic, thin shrink small outline package; 24 leads; 0.65 mm pitch; 7.8 mm x 4.4 mm x 1.1 mm bodyPackage information2022-06-22
SOT815-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 24 terminals; 0.5 mm pitch; 5.5 mm x 3.5 mm x 1 mm bodyPackage information2021-08-17

支持

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模型

文件名称标题类型日期
axp8t24574AXP8T245 IBIS modelIBIS model2020-11-20

订购、定价与供货

样品

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