74LVC2G07GW

Buffers with open-drain outputs

The 74LVC2G07 provides two non-inverting buffers.

The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant input/output for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • -24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

目标应用

参数类型

型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G07GWProduction1.65 - 5.5CMOS/LVTTL321752low-40~12526438.4153TSSOP6

Package

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74LVC2G07GW
TSSOP6
(SOT363)
SOT363Reel 7" Q3/T4, ReverseActiveStandard Marking74LVC2G07GW,125
( 9352 741 65125 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期EFRIFRMTBF(小时)MSLMSL无铅
74LVC2G07GW74LVC2G07GW,12574LVC2G07GWAlways Pb-free123.83.872.58E811
品质及可靠性免责声明

文档 (8)

文件名称标题类型日期
74LVC2G07Buffers with open-drain outputsData sheet2017-08-21
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2011-02-04
AN212Package lead inductance considerations in high-speed applicationsApplication note2013-03-13
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
lvc2g0774LVC2G07 IBIS modelIBIS model2015-09-06
SOT363_125Tape reel SMD; reversed product orientation 12NC ending 125Packing2012-11-20
SOT363plastic, surface-mounted package; 6 leads; 1.3 mm pitch; 2 mm x 1.25 mm x 0.95 mm bodyOutline drawing2018-02-23

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模型

文件名称标题类型日期
lvc2g0774LVC2G07 IBIS modelIBIS model2015-09-06

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