74LVC2G16GF NRND

Dual buffer gate

The 74LVC2G16 provides two buffers.

Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Not recommended for new designs (NRND), 单击此处 for the alternative product.

特性

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant inputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.

目标应用

参数类型

型号Product statusPackage name
74LVC2G16GF
NRND
Not for design inXSON6

Package

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74LVC2G16GF
NRND

XSON6
(SOT891)
SOT891Reel 7" Q3/T4, ReverseActiveStandard Marking74LVC2G16GFH
( 9353 075 99125 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期MSLMSL无铅
74LVC2G16GF
NRND
74LVC2G16GFH74LVC2G16GFAlways Pb-free11
品质及可靠性免责声明

文档 (3)

文件名称标题类型日期
74LVC2G16Dual buffer gateData sheet2017-03-17
lvc2g1674LVC2G16 IBIS modelIBIS model2015-11-01
SOT891plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm bodyOutline drawing2018-10-18

支持

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模型

文件名称标题类型日期
lvc2g1674LVC2G16 IBIS modelIBIS model2015-11-01

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