74LVC1G97GS

Low-power configurable multiple function gate

The 74LVC1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected to VCC or GND.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant input/output for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V).
  • ±24 mA output drive (VCC = 3.0 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.

目标应用

参数类型

型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G97GSProduction1.65 - 5.5TTL+/- 326.31501low-40~12531326.6209XSON6

Package

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74LVC1G97GS
XSON6
(SOT1202)
SOT1202Reel 7" Q1/T1, Q3/T4ActiveYV74LVC1G97GS,132
( 9352 931 88132 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期EFRIFRMTBF(小时)MSLMSL无铅
74LVC1G97GS74LVC1G97GS,13274LVC1G97GSAlways Pb-free123.83.872.58E811
品质及可靠性免责声明

文档 (8)

文件名称标题类型日期
74LVC1G97Low-power configurable multiple function gateData sheet2017-03-17
AN10343MicroPak soldering informationApplication note2010-12-30
AN11009Pin FMEA for LVC familyApplication note2011-02-04
AN212Package lead inductance considerations in high-speed applicationsApplication note2013-03-13
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
lvc1g9774LVC1G97 IBIS modelIBIS model2014-10-20
SOT1202_132Reversed product orientation 12NC ending 132Packing2013-04-04
SOT1202plastic, leadless extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1mm x 0.35 mm bodyOutline drawing2018-06-04

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模型

文件名称标题类型日期
lvc1g9774LVC1G97 IBIS modelIBIS model2014-10-20

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