74AUP1T45GW

Low-power dual supply translating transceiver; 3-state

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (V_CC(A) and V_CC(B)) which enable bidirectional level translation. Both V_CC(A) and V_CC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to V_CC(A) and pin B is referenced to V_CC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire V_CC(A) and V_CC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND, both A and B are in the high-impedance OFF-state.

特性

Wide supply voltage range:
- V_CC(A): 1.1 V to 3.6 V
- V_CC(B): 1.1 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I_CC = 0.9 μA (maximum)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial power-down mode operation
Multiple package options
Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

目标应用

参数类型

型号	Product status	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1T45GW	Production	1.1 - 3.6	1.1 - 3.6	CMOS	+/- 1.9	15.6	1	ultra low	-40~125	270	43.3	158	TSSOP6

Package

型号	封装	尺寸版本	回流焊/波峰焊	包装	状态	标示	可订购的器件编号，（订购码(12NC)）
74AUP1T45GW	TSSOP6 (SOT363)	SOT363		Reel 7" Q3/T4, Reverse	Active	p5	74AUP1T45GW,125 ( 9352 805 13125 )

品质、可靠性及化学成分

型号	可订购的器件编号	化学成分	RoHS / RHF	无铅转换日期	MSL	MSL无铅
74AUP1T45GW	74AUP1T45GW,125	74AUP1T45GW		Always Pb-free	1	1

品质及可靠性免责声明

系列

74AUP1T45 - Low-power dual supply translating transceiver; 3-state

文档 (7)

文件名称	标题	类型	日期
74AUP1T45	Low-power dual supply translating transceiver; 3-state	Data sheet	2017-05-03
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN10156	Sorting through the low voltage logic maze	Application note	2013-03-13
Nexperia_document_guide_Logic_translators_201711	Nexperia Logic Translators	Brochure	2017-12-05
aup1t45	aup1t45 IBIS model	IBIS model	2014-12-21
SOT363_125	Tape reel SMD; reversed product orientation 12NC ending 125	Packing	2012-11-20
SOT363	plastic, surface-mounted package; 6 leads; 1.3 mm pitch; 2 mm x 1.25 mm x 0.95 mm body	Outline drawing	2018-10-18

支持

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模型

文件名称	标题	类型	日期
aup1t45	aup1t45 IBIS model	IBIS model	2014-12-21

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