Nexperia

74AUP1T45GW

Low-power dual supply translating transceiver; 3-state

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND, both A and B are in the high-impedance OFF-state.

特性

  • Wide supply voltage range:
    • VCC(A): 1.1 V to 3.6 V
    • VCC(B): 1.1 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

目标应用

参数类型

型号Product statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1T45GWProduction1.1 - 3.61.1 - 3.6CMOS+/- 1.915.61ultra low-40~12527043.3158TSSOP6

Package

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AUP1T45GW
TSSOP6
(SOT363) 		SOT363Reel 7" Q3/T4, ReverseActivep574AUP1T45GW,125
( 9352 805 13125 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期MSLMSL无铅
74AUP1T45GW74AUP1T45GW,12574AUP1T45GWAlways Pb-free11
品质及可靠性免责声明

系列

文档 (8)

文件名称标题类型日期
74AUP1T45Low-power dual supply translating transceiver; 3-stateData sheet2017-05-03
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
Nexperia_document_guide_Logic_translators_201711Nexperia Logic TranslatorsBrochure2017-12-05
aup1t45aup1t45 IBIS modelIBIS model2014-12-21
75017285Logic selection guide 2016Selection guide2015-01-07
SOT363_125Tape reel SMD; reversed product orientation 12NC ending 125Packing2012-11-20
SOT363plastic, surface-mounted package; 6 leads; 1.3 mm pitch; 2 mm x 1.25 mm x 0.95 mm bodyOutline drawing2018-02-23

支持

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模型

文件名称标题类型日期
aup1t45aup1t45 IBIS modelIBIS model2014-12-21

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