74AVC4TD245GU

4-bit dual supply translating transceiver with configurable voltage translation; 3-state

The 74AVC4TD245 is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

特性

  • Wide supply voltage range:
    • VCC(A): 0.8 V to 3.6 V
    • VCC(B): 0.8 V to 3.6 V
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114E Class 3B exceeds 8000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101C exceeds 1000 V
  • Maximum data rates:
    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

目标应用

参数类型

型号Product statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AVC4TD245GUProduction0.8 - 3.60.8 - 3.6CMOS/LVTTL+/- 122.14very low-40~125994.289XQFN16

Package

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74AVC4TD245GU
XQFN16
(SOT1161-1)
SOT1161-1Reel 7" Q1/T1ActiveStandard Marking74AVC4TD245GU,115
( 9352 941 68115 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期MSLMSL无铅
74AVC4TD245GU74AVC4TD245GU,11574AVC4TD245GUAlways Pb-free11
品质及可靠性免责声明

文档 (7)

文件名称标题类型日期
74AVC4TD2454-bit dual supply translating transceiver with configurable voltage translation; 3-stateData sheet2017-06-09
AN252Live Insertion Aspects of Philips Logic FamiliesApplication note2013-03-13
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
Nexperia_document_guide_Logic_translators_201711Nexperia Logic TranslatorsBrochure2017-12-05
avc4td245avc4td245 IBIS modelIBIS model2013-04-07
SOT1161-1_115Standard product orientation 12NC ending 115Packing2013-04-05
SOT1161-1plastic, leadless extermely thin quad flat package; 16 terminals; 0.4 mm pitch; 1.8 mm x 2.6 mm x 0.5 mm bodyOutline drawing2018-06-03

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模型

文件名称标题类型日期
avc4td245avc4td245 IBIS modelIBIS model2013-04-07

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