74AXP1G00 NRND

Low-power 2-input NAND gate

The 74AXP1G00 is a single 2-input NAND gate.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

不建议用在新设计中(NRND)。

特性

Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; C_I = 0.5 pF (typical)
Low output capacitance; C_O = 1.0 pF (typical)
Low dynamic power consumption; C_PD = 2.5 pF at V_CC = 1.2 V (typical)
Low static power consumption; I_CC = 0.6 μA (85 °C maximum)
High noise immunity
Complies with JEDEC standard:
- JESD8-12A.01 (1.1 V to 1.3 V)
- JESD8-11A.01 (1.4 V to 1.6 V)
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
- CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C

文档 (5)

文件名称	标题	类型	日期
74AXP1G00	Low-power 2-input NAND gate	Data sheet	2021-07-06
axp1g00	74AXP1G00 IBIS model	IBIS model	2014-10-22
Nexperia_document_leaflet_Logic_X2SON_packages_062018	X2SON ultra-small 4, 5, 6 & 8-pin leadless packages	Leaflet	2018-06-05
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904	AXP – Extremely low-power logic technology portfolio	Leaflet	2019-04-05
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10

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模型

文件名称	标题	类型	日期
axp1g00	74AXP1G00 IBIS model	IBIS model	2014-10-22