PDI1284P11

3.3 V parallel interface transceiver/buffer

The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19 signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to interface 3.3 V or 5.0 V devices.

The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR.

The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs, depending on the state of the high drive enable pin HD. The A-bus has only totem pole style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at V_CC = 3.3 V.

特性

Asynchronous operation
8-bit transceivers
Six additional buffer/driver lines peripheral to cable
Five additional control lines from cable
5 V tolerant
ESD protection:
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Latch-up current protection exceeds 500 mA per JEDEC Std 19
Input hysteresis
Low-noise operation
IEEE 1284 compliant level 1 and 2
Overvoltage protection on B/Y side for off-state
A side 3-state option
B side active or resistive pull-up option
Cable side supply voltage for 5 V or 3 V operation

文档 (2)

文件名称	标题	类型	日期
PDI1284P11	3.3 V parallel interface transceiver/buffer	Data sheet	2021-07-06
AN263	Power considerations when using CMOS and BiCMOS logic devices	Application note	2023-02-07

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