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74LVC157A-Q100

Quad 2-input multiplexer

the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E) is active LOW. When pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74LVC157A. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator.

It is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common.

The device is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

  • 5 V tolerant inputs for interfacing with 5 V logic

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power consumption

  • Direct interface with TTL levels

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC157ABQ-Q100Production1.2 - 3.6CMOS/LVTTL± 242.5low-40~1259414.964DHVQFN16
74LVC157AD-Q100Production1.2 - 3.6CMOS/LVTTL± 242.5low-40~1259310.353.3SO16
74LVC157APW-Q100Production1.2 - 3.6CMOS/LVTTL± 242.5low-40~1251264.956.4TSSOP16

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74LVC157ABQ-Q100
DHVQFN16
(SOT763-1)
SOT763-1SOT763-1_115ActiveVC157A74LVC157ABQ-Q100X
( 9352 992 78115 )
74LVC157AD-Q100
SO16
(SOT109-1)
SOT109-1SO-SOJ-REFLOW
SO-SOJ-WAVE
SOT109-1_118Active74LVC157AD74LVC157AD-Q100J
( 9352 992 79118 )
74LVC157APW-Q100
TSSOP16
(SOT403-1)
SOT403-1SSOP-TSSOP-VSO-WAVE
SOT403-1_118ActiveLVC157A74LVC157APW-Q100J
( 9352 992 81118 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC157ABQ-Q10074LVC157ABQ-Q100X74LVC157ABQ-Q100Always Pb-free
74LVC157AD-Q10074LVC157AD-Q100J74LVC157AD-Q100Always Pb-free
74LVC157APW-Q10074LVC157APW-Q100J74LVC157APW-Q100Always Pb-free
品质及可靠性免责声明

文档 (13)

文件名称标题类型日期
74LVC157A_Q100Quad 2-input multiplexerData sheet2024-02-12
AN263Power considerations when using CMOS and BiCMOS logic devicesApplication note2023-02-07
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc157alvc157a IBIS modelIBIS model2013-04-07
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
lvclvc Spice modelSPICE model2013-05-06
SOT763-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 1 mm bodyPackage information2023-05-11
SO-SOJ-WAVEFootprint for wave solderingWave soldering2009-10-08
SO-SOJ-REFLOWFootprint for reflow solderingReflow soldering2009-10-08
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08
SOT109-1plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.75 mm bodyPackage information2023-11-07
SOT403-1plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.2 mm bodyPackage information2023-11-08
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08

支持

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模型

文件名称标题类型日期
lvc157alvc157a IBIS modelIBIS model2013-04-07
lvclvc Spice modelSPICE model2013-05-06

样品

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