双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVC164245

16-bit dual supply translating transceiver; 3-state

The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.

This device can be used as two 8-bit transceivers or one 16-bit transceiver.

The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).

In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode).

Features and benefits

  • Wide supply voltage range:

    • 3 V port (VCC(A)): 1.5 V to 3.6 V

    • 5 V port (VCC(B)): 1.5 V to 5.5 V

  • CMOS low power consumption

  • Overvoltage tolerant inputs to 5.5 V

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Control inputs voltage range from 2.7 V to 5.5 V

  • High-impedance outputs when VCC(A) or VCC(B) = 0 V

  • Complies with JEDEC standards:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name Category
74ALVC164245DGG 1.5 - 5.5 1.5 - 3.6 CMOS/LVTTL ± 24 2.9 16 low -40~85 82 2 37 TSSOP48 Bidirectional | Direction controlled
74ALVC164245DGG-Q100 n.a. CMOS/LVTTL ± 24 16 low -40~85 82 2 37 TSSOP48

封装

型号 可订购的器件编号,(订购码(12NC)) 状态 标示 封装 外形图 回流焊/波峰焊 包装
74ALVC164245DGG 74ALVC164245DGG:11
(935202350118)
Active ALVC164245 SOT362-1
TSSOP48
(SOT362-1)
SOT362-1 SSOP-TSSOP-VSO-WAVE
SOT362-1_118
74ALVC164245DGG-Q100 74ALVC164245DGG‑QJ
(935300761118)
Active ALVC164245 SOT362-1
TSSOP48
(SOT362-1)
SOT362-1 SSOP-TSSOP-VSO-WAVE
SOT362-1_118

下表中的所有产品型号均已停产 。

型号 可订购的器件编号,(订购码(12NC)) 状态 标示 封装 外形图 回流焊/波峰焊 包装
74ALVC164245BX 74ALVC164245BX,518
(935295865518)
Obsolete ALVC164245 Standard Procedure Standard Procedure no package information
74ALVC164245DL 74ALVC164245DL,112
(935202340112)
Obsolete ALVC164245 SOT370-1
SSOP48
(SOT370-1)
SOT370-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暂无信息
74ALVC164245DL,118
(935202340118)
Withdrawn / End-of-life ALVC164245 SOT370-1_118

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74ALVC164245DGG 74ALVC164245DGG:11 74ALVC164245DGG rohs rhf rhf
74ALVC164245DGG-Q100 74ALVC164245DGG‑QJ 74ALVC164245DGG-Q100 rohs rhf rhf

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74ALVC164245BX 74ALVC164245BX,518 74ALVC164245BX rohs rhf rhf
74ALVC164245DL 74ALVC164245DL,112 74ALVC164245DL rohs rhf rhf
74ALVC164245DL 74ALVC164245DL,118 74ALVC164245DL rohs rhf rhf
品质及可靠性免责声明

文档 (12)

文件名称 标题 类型 日期
74ALVC164245 16-bit dual supply translating transceiver; 3-state Data sheet 2024-04-24
AN90063 Questions about package outline drawings Application note 2025-10-22
001aaa789 Block diagram: 74ALVC16245DGG, 74ALVC16245DL, 74ALVC164245BQ, 74ALVC164245DGG, 74ALVC164245DL, 74ALVCH16245DGG, 74ALVCH16245DL, 74LVT16245BBQ, 74LVT16245BDGG, 74LVT16245BDL, 74LVT16245BEV, 74LVTH16245BBQ, 74LVTH16245BDGG, 74LVTH16245BDL, 74LVTN16245BBQ, 74LVTN16245BDGG Block diagram 2009-11-04
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
SOT362-1 3D model for products with SOT362-1 package Design support 2020-01-22
alvc164245 alvc164245 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP48_SOT362-1_mk plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body Marcom graphics 2017-01-28
SOT362-1 plastic thin shrink small outline package; 48 leads; body width 6.1 mm Package information 2024-01-05
SOT370-1 plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名称 标题 类型 日期
SOT362-1 3D model for products with SOT362-1 package Design support 2020-01-22
alvc164245 alvc164245 IBIS model IBIS model 2013-04-08

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