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74LVC3G16

Triple buffer

The 74LVC3G16 provides three buffers.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G16 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant input/output for interfacing with 5 V logic

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8B/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Rth(j-c) (K/W)Package name
74LVC3G16DPProduction1.65 - 5.5CMOS/LVTTL± 321753low-40~125217106TSSOP8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC3G16DP
TSSOP8
(SOT505-2) 		SOT505-2SOT505-2_125ActiveYU74LVC3G16DPH
( 9353 076 06125 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC3G16DP74LVC3G16DPH74LVC3G16DPAlways Pb-free
品质及可靠性免责声明

文档 (4)

文件名称标题类型日期
74LVC3G16Triple bufferData sheet2023-08-29
lvc3g1674LVC3G16 IBIS modelIBIS model2015-11-08
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2022-06-03

支持

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模型

文件名称标题类型日期
lvc3g1674LVC3G16 IBIS modelIBIS model2015-11-08

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样品

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