双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)
SOT364-1

74ALVCH16543

16-bit D-type registered transceiver; 3-state

TThe 74ALVCH16543 is a 16-bit registered transceiver with bus hold inputs and 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

Data flow in each direction is controlled by intput enable (nEAB and nEBA), latch enable (nLEAB and nLEBA), and output enable (nOEAB and nOEBA) inputs. For A to B data flow, the device operates in the transparen mode when (nEAB) and (nLEAB) are LOW. A subsequent LOW-to-HIGH transition of the nLEAB input latches the data and the outputs no longer change with the inputs. A HIGH on either nEAB or nOEAB causes the outputs to assume a high-impedance OFF-state.

Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • MULTIBYTE™ flow-through standard pin-out architecture

  • Back-to-back registers for storage

  • Output drive capability 50 Ω transmission lines at 85 °C

  • All data inputs have bushold

  • Low inductance multiple VCC and GND pins for minimize noise and ground bounce

  • Current drive ±24 mA at VCC = 3.0 V.

  • 3-state non-inverting outputs for bus oriented applications

  • Complies with JEDEC standards:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits fmax (MHz) Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Package name
74ALVCH16543DGG n.a. n.a. TTL ± 24 3.8 16 150 low -40~85 93 TSSOP56

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74ALVCH16543DGG 74ALVCH16543DGG,11
(935262544118)		 Active ALVCH16543 SOT364-1
TSSOP56
(SOT364-1) 		SOT364-1 SSOP-TSSOP-VSO-WAVE
SOT364-1_118

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74ALVCH16543DGG 74ALVCH16543DGG,11 74ALVCH16543DGG rohs rhf rhf
品质及可靠性免责声明

文档 (8)

文件名称 标题 类型 日期
74ALVCH16543 16-bit D-type registered transceiver; 3-state Data sheet 2024-07-03
AN90063 Questions about package outline drawings Application note 2025-06-13
mna301 Block diagram: 74ALVCH16543DGG Block diagram 2009-11-03
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
alvch16543 alvch16543 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名称 标题 类型 日期
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
alvch16543 alvch16543 IBIS model IBIS model 2013-04-08

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