74LVC1G07-Q100
Buffer with open-drain output
The 74LVC1G07-Q100 is a single buffer with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power consumption
IOFF circuitry provides partial Power-down mode operation
-24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
参数类型
| 型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G07GS-Q100 | 1.65 - 5.5 | CMOS/LVTTL | 32 | 175 | 1 | low | -40~125 | 341 | 34.6 | 231 | XSON6 |
| 74LVC1G07GV-Q100 | 1.65 - 5.5 | CMOS/LVTTL | 32 | 175 | 1 | low | -40~125 | 278 | 68.5 | 175 | TSOP5 |
| 74LVC1G07GW-Q100 | 1.65 - 5.5 | CMOS/LVTTL | 32 | 175 | 1 | low | -40~125 | 319 | 88 | 188 | TSSOP5 |
| 74LVC1G07GZ-Q100 | 1.65 - 5.5 | CMOS/LVTTL | low | -40~125 | XSON5 |
封装
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74LVC1G07GS-Q100 | 74LVC1G07GS-Q100H (935690778125) |
Active | VS |
XSON6 (SOT1202) |
SOT1202 |
REFLOW_BG-BD-1
|
暂无信息 |
| 74LVC1G07GV-Q100 | 74LVC1G07GV-Q100H (935300906125) |
Active | V07 |
TSOP5 (SOT753) |
SOT753 |
REFLOW_BG-BD-1
WAVE_BG-BD-1 |
SOT753_125 |
| 74LVC1G07GW-Q100 | 74LVC1G07GW-Q100H (935300907125) |
Active | VS |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
| 74LVC1G07GZ-Q100 | 74LVC1G07GZ-Q100YL (935691694315) |
Active | VS |
XSON5 (SOT8065-1) |
SOT8065-1 | SOT8065-1_315 |
环境信息
| 型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC1G07GS-Q100 | 74LVC1G07GS-Q100H | 74LVC1G07GS-Q100 |
|
|
| 74LVC1G07GV-Q100 | 74LVC1G07GV-Q100H | 74LVC1G07GV-Q100 |
|
|
| 74LVC1G07GW-Q100 | 74LVC1G07GW-Q100H | 74LVC1G07GW-Q100 |
|
|
| 74LVC1G07GZ-Q100 | 74LVC1G07GZ-Q100YL | 74LVC1G07GZ-Q100 |
|
|
文档 (23)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74LVC1G07_Q100 | Buffer with open-drain output | Data sheet | 2024-09-23 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-06-13 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT1202 | 3D model for products with SOT1202 package | Design support | 2023-02-02 |
| SOT753 | 3D model for products with SOT753 package | Design support | 2019-01-22 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT8065-1 | 3D model for products with SOT8065-1 package | Design support | 2024-11-05 |
| lvc1g07 | 74LVC1G07 IBIS model | IBIS model | 2018-05-25 |
| Nexperia_document_leaflet_Logic_X2SON_packages_062018 | X2SON ultra-small 4, 5, 6 & 8-pin leadless packages | Leaflet | 2018-06-05 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| Leaflet_SOT8065_Minilogic | Leaflet_SOT8065 Minilogic | Leaflet | 2024-11-15 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT1202 | plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1mm x 0.35 mm body | Package information | 2022-06-01 |
| SOT753 | plastic, surface-mounted package; 5 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body | Package information | 2022-05-31 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| SOT8065-1 | Plastic thermal enhanced extremely thin small outline package withside-wettable flanks (SWF); no leads; 5 terminals; body 1.1 × 0.85 × 0.5mm | Package information | 2024-08-28 |
| REFLOW_BG-BD-1 | Reflow soldering profile | Reflow soldering | 2021-04-06 |
| MAR_SOT1202 | MAR_SOT1202 Topmark | Top marking | 2013-06-03 |
| MAR_SOT753 | MAR_SOT753 Topmark | Top marking | 2013-06-03 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
支持
如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。
模型
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| SOT1202 | 3D model for products with SOT1202 package | Design support | 2023-02-02 |
| SOT753 | 3D model for products with SOT753 package | Design support | 2019-01-22 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| SOT8065-1 | 3D model for products with SOT8065-1 package | Design support | 2024-11-05 |
| lvc1g07 | 74LVC1G07 IBIS model | IBIS model | 2018-05-25 |
Ordering, pricing & availability
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