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74ALVCH16600DGG

18-bit universal bus transceiver; 3-state

The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The HIGH clock can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B, but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74ALVCH16600DGG 74ALVCH16600DGGY 935262545518 SOT364-1 订单产品

特性

  • CMOS low power consumption
  • MultiByte flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce
  • Direct interface with TTL levels (2.7 V to 3.6 V)
  • Bus hold on data inputs
  • Output drive capability 50 Ω transmission lines at 85 °C
  • Current drive ±24 mA at 3.0 V
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    • CDM JESD22-C101E exceeds 1000 V

目标应用

参数类型

型号Product statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsfmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Package name
74ALVCH16600DGGProduction1.65 - 3.6n.a.TTL± 242.818150low-40~8593TSSOP56

Package

型号可订购的器件编号,(订购码(12NC))状态标示封装尺寸版本回流焊/波峰焊包装
74ALVCH16600DGG74ALVCH16600DGG:11
( 9352 625 45118 )
DevelopmentALVCH16600
TSSOP56
(SOT364-1)
SOT364-1SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1
74ALVCH16600DGGY
( 9352 625 45518 )
ActiveALVCH16600Reel 13" Q1/T1 in Drypack

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHFMSLMSL无铅
74ALVCH16600DGG74ALVCH16600DGG:1174ALVCH16600DGG11
74ALVCH16600DGG74ALVCH16600DGGY74ALVCH16600DGG22
品质及可靠性免责声明

文档 (4)

文件名称标题类型日期
74ALVCH1660018-bit universal bus transceiver; 3-stateData sheet2018-01-15
alvch16600alvch16600 IBIS modelIBIS model2013-04-07
74ALVCH16600DGG_Nexperia_Product_Reliability74ALVCH16600DGG Nexperia Product ReliabilityQuality document2022-05-04
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08

支持

如果您需要设计/技术支持,请告知我们并填写 应答表, 我们会尽快回复您。

模型

文件名称标题类型日期
alvch16600alvch16600 IBIS modelIBIS model2013-04-07

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装Packing quantity在线购买
74ALVCH16600DGG74ALVCH16600DGGY935262545518Reel 13" Q1/T1 in Drypack- 订单产品

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品: https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号,我们的全球与区域经销网络可以协助您取得样品。