Register once, drag and drop ECAD models into your CAD tool and speed up your design.

Click here for more information

74ALVCH16601DGG ECAD models PCB Symbol, Footprint & ECAD Model

18-bit universal bus transceiver (3-State)

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE AB and OE BA) latch enable (LEAB and LEBA ) , and clock (CPAB and CPBA) inputs. For A-to-B data flowthe device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OE AB is Low, the outputs are active. When OE AB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CE BA /CE AB).

Data flow for B-to-A is similar to that of A-to-B but uses OE BA LEBA and CPBA.

To ensure the high impedance state during power up or power down, OE BA and OE AB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74ALVCH16601DGG 74ALVCH16601DGGS 935262546512 SOT364-1 订单产品
74ALVCH16601DGG 74ALVCH16601DGGY 935262546518 SOT364-1 订单产品
74ALVCH16601DGG 74ALVCH16601DGG,11 935262546112 SOT364-1 订单产品
74ALVCH16601DGG 74ALVCH16601DGG:11 935262546118 SOT364-1 订单产品

特性

  • Complies with JEDEC standard no. 8-1A
  • CMOS low power consumption
  • Direct interface with TTL levels
  • MULTIBYTE™™ flow-through standard pin-out architecture
  • Low inductance multiple VCC and ground pins for minimum noise and ground bounce
  • Current drive ±24 mA at 3.0 V
  • All inputs have bus hold circuitry
  • Output drive capability 50 Ω transmission lines @ 85 °C

目标应用

参数类型

型号Product statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capabilitytpd (ns)No of bitsfmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVCH16601DGGProduction1.65 - 3.6n.a.TTL+/- 242.818150low-40~859321.0TSSOP56

Package

型号可订购的器件编号,(订购码(12NC))状态标示封装尺寸版本回流焊/波峰焊包装
74ALVCH16601DGG74ALVCH16601DGGS
( 9352 625 46512 )
ActiveALVCH16601
TSSOP56
(SOT364-1)
SOT364-1SSOP-TSSOP-VSO-WAVE
Tube in Drypack
74ALVCH16601DGGY
( 9352 625 46518 )
ActiveALVCH16601Reel 13" Q1/T1 in Drypack

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHFEFRIFRMTBF(小时)MSLMSL无铅
74ALVCH16601DGG74ALVCH16601DGGS74ALVCH16601DGG123.83.872.58E822
74ALVCH16601DGG74ALVCH16601DGGY74ALVCH16601DGG123.83.872.58E822
品质及可靠性免责声明

文档 (5)

文件名称标题类型日期
74ALVCH1660118-bit universal bus transceiver; 3-stateData sheet2018-08-14
alvch16601alvch16601 IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT364-1_118TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-15
SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyOutline drawing2018-10-18

支持

如果您需要设计/技术支持,请告知我们并填写 应答表, 我们会尽快回复您。

模型

文件名称标题类型日期
alvch16601alvch16601 IBIS modelIBIS model2013-04-07

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装在线购买
74ALVCH16601DGG74ALVCH16601DGGS935262546512Tube in Drypack订单产品
74ALVCH16601DGG74ALVCH16601DGGY935262546518Reel 13" Q1/T1 in Drypack订单产品
74ALVCH16601DGG74ALVCH16601DGG,11935262546112Bulk Pack订单产品
74ALVCH16601DGG74ALVCH16601DGG:11935262546118Reel 13" Q1/T1订单产品

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品: https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号,我们的全球与区域经销网络可以协助您取得样品。