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74ALVCH16652DGG

16-bit transceiver/register with dual enable; 3-state

The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.

Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable (nOEAB and nOEBA) control inputs.

Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating mode.

The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver. When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is HIGH, no data transmission from nBn to nAn is possible.

When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this configuration each output reinforces its input.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74ALVCH16652DGG 74ALVCH16652DGGY 935262799518 SOT364-1 订单产品

特性

  • Wide supply voltage range of 1.2 V to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Current drive ±24 mA at VCC = 3.0 V.
  • MULTIBYTE flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce
  • All data inputs have bushold
  • Output drive capability 50 Ω transmission lines at 85 °C
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    • CDM JESD22-C101E exceeds 1000 V

目标应用

参数类型

型号Product statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsfmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Package name
74ALVCH16652DGGProduction1.65 - 3.6n.a.TTL± 242.616150low-40~8593TSSOP56

Package

型号可订购的器件编号,(订购码(12NC))状态标示封装尺寸版本回流焊/波峰焊包装
74ALVCH16652DGG74ALVCH16652DGG,11
( 9352 627 99118 )
DevelopmentALVCH16652
TSSOP56
(SOT364-1)
SOT364-1SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1
74ALVCH16652DGGY
( 9352 627 99518 )
ActiveALVCH16652Reel 13" Q1/T1 in Drypack

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHFMSLMSL无铅
74ALVCH16652DGG74ALVCH16652DGG,1174ALVCH16652DGG11
74ALVCH16652DGG74ALVCH16652DGGY74ALVCH16652DGG22
品质及可靠性免责声明

文档 (4)

文件名称标题类型日期
74ALVCH1665216-bit transceiver/register with dual enable; 3-stateData sheet2018-09-12
alvch16652alvch16652 IBIS modelIBIS model2013-04-07
74ALVCH16652DGG_Nexperia_Product_Reliability74ALVCH16652DGG Nexperia Product ReliabilityQuality document2022-05-04
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08

支持

如果您需要设计/技术支持,请告知我们并填写 应答表, 我们会尽快回复您。

模型

文件名称标题类型日期
alvch16652alvch16652 IBIS modelIBIS model2013-04-07

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装Packing quantity在线购买
74ALVCH16652DGG74ALVCH16652DGGY935262799518Reel 13" Q1/T1 in Drypack- 订单产品

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品: https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号,我们的全球与区域经销网络可以协助您取得样品。