74ALVCH16601

18-bit universal bus transceiver; 3-state

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

特性

  • CMOS low power consumption
  • MultiByte flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • Bus hold on data inputs
  • Output drive capability 50 Ω transmission lines at 85 °C
  • Current drive ±24 mA at 3.0 V
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    • CDM JESD22-C101E exceeds 1000 V

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capabilitytpd (ns)No of bitsfmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVCH16601DGGProduction1.65 - 3.6n.a.TTL+/- 242.818150low-40~859321.0TSSOP56

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74ALVCH16601DGG
TSSOP56
(SOT364-1)
SOT364-1SSOP-TSSOP-VSO-WAVE
Tube in DrypackActiveALVCH1660174ALVCH16601DGGS
( 9352 625 46512 )
Reel 13" Q1/T1 in DrypackActiveALVCH1660174ALVCH16601DGGY
( 9352 625 46518 )

停产信息

型号可订购的器件编号,(订购码(12NC))最后一次购买日期最后一次交货日期替代产品状态备注
74ALVCH16601DGG935262546112
74ALVCH16601DGG935262546118

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期EFRIFRMTBF(小时)MSLMSL无铅
74ALVCH16601DGG74ALVCH16601DGGS74ALVCH16601DGGAlways Pb-free123.83.872.58E822
74ALVCH16601DGG74ALVCH16601DGGY74ALVCH16601DGGAlways Pb-free123.83.872.58E822
品质及可靠性免责声明

文档 (5)

文件名称标题类型日期
74ALVCH1660118-bit universal bus transceiver; 3-stateData sheet2018-08-14
alvch16601alvch16601 IBIS modelIBIS model2013-04-07
SOT364-1_118TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-15
SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyOutline drawing2018-10-18
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08

支持

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模型

文件名称标题类型日期
alvch16601alvch16601 IBIS modelIBIS model2013-04-07

订购、定价与供货

样品

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