74AUP1G0832

Low-power 3-input AND-OR gate

The 74AUP1G0832 is a single 3-input AND-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性

Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Low static power consumption; I_CC = 0.9 μA (maximum)
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type number	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP1G0832GM	Production	0.8 - 3.6	CMOS	± 1.9	6.7	70	1	ultra low	-40~125	290	6.5	145	XSON6
74AUP1G0832GN	Production	0.8 - 3.6	CMOS	± 1.9	6.7	70	1	ultra low	-40~125	275	11.7	171	XSON6
74AUP1G0832GS	Production	0.8 - 3.6	CMOS	± 1.9	6.7	70	1	ultra low	-40~125	272	14.8	177	XSON6
74AUP1G0832GW	Production	0.8 - 3.6	CMOS	± 1.9	6.7	70	1	ultra low	-40~125	264	38.6	153	TSSOP6

封装

型号	封装	包装	状态	标示	可订购的器件编号，（订购码(12NC)）
74AUP1G0832GM	XSON6 (SOT886)	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GM,132 ( 9352 806 19132 )
74AUP1G0832GM	XSON6 (SOT886)	Reel 7” Q1/T1 or Q2/T3	Active	aY	74AUP1G0832GM,115 ( 9352 806 19115 )
74AUP1G0832GN	XSON6 (SOT1115)	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GN,132 ( 9352 917 17132 )
74AUP1G0832GS	XSON6 (SOT1202)	Reel 7" Q1/T1, Q3/T4	Active	aY	74AUP1G0832GS,132 ( 9352 928 32132 )
74AUP1G0832GW	TSSOP6 (SOT363-2)	Reel 7" Q3/T4, Reverse	Active	aY	74AUP1G0832GW,125 ( 9352 806 18125 )

品质、可靠性及化学成分

型号	可订购的器件编号	化学成分	无铅转换日期	EFR	IFR	MTBF（小时）	MSL	MSL无铅
74AUP1G0832GM	74AUP1G0832GM,132	74AUP1G0832GM	Always Pb-free	33.0	1	1.07E9	1	1
74AUP1G0832GM	74AUP1G0832GM,115	74AUP1G0832GM	Always Pb-free	33.0	1	1.07E9	1	1
74AUP1G0832GN	74AUP1G0832GN,132	74AUP1G0832GN	Always Pb-free	33.0	1	1.07E9	1	1
74AUP1G0832GS	74AUP1G0832GS,132	74AUP1G0832GS	Always Pb-free	33.0	1	1.07E9	1	1
74AUP1G0832GW	74AUP1G0832GW,125	74AUP1G0832GW	Always Pb-free	33.0	1	1.07E9	1	1

品质及可靠性免责声明

文档 (10)

文件名称	标题	类型	日期
74AUP1G0832	Low-power 3-input AND-OR gate	Data sheet	2022-01-18
AN10161	PicoGate Logic footprints	Application note	2002-10-29
AN11052	Pin FMEA for AUP family	Application note	2019-01-09
aup1g0832	aup1g0832 IBIS model	IBIS model	2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904	Leaflet	2019-04-12
Nexperia_document_Logic_CombinationLogic_infocard_201710	Combination logic solutions card	Leaflet	2017-10-16
Nexperia_Selection_guide_2022	Nexperia Selection Guide 2022	Selection guide	2022-01-05
MAR_SOT1202	MAR_SOT1202 Topmark	Top marking	2013-06-03
MAR_SOT1115	MAR_SOT1115 Topmark	Top marking	2013-06-03
MAR_SOT886	MAR_SOT886 Topmark	Top marking	2013-06-03

支持

在此页面中寻找您的设计问题答案。如有提供，您可以在我们的安世半导体支持社区找到相关信息，或者您可以找到安世半导体模型和设计工具。

模型

文件名称	标题	类型	日期
aup1g0832	aup1g0832 IBIS model	IBIS model	2014-12-21

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样品

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