×

74AUP1G885

Low-power dual function gate

The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G885DCProduction0.8 - 3.6CMOS± 1.97.6701ultra low-40~12520334.1113VSSOP8
74AUP1G885GFNot for design inXSON8
74AUP1G885GNProduction0.8 - 3.6CMOS± 1.97.6701ultra low-40~12523810.6148XSON8
74AUP1G885GSProduction0.8 - 3.6CMOS± 1.97.6701ultra low-40~12527610.8146XSON8
74AUP1G885GTProduction0.8 - 3.6CMOS± 1.97.6701ultra low-40~1253276.1157XSON8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74AUP1G885DC
VSSOP8
(SOT765-1)
Reel 7" Q3/T4, ReverseActivepS874AUP1G885DC,125
( 9352 807 65125 )
74AUP1G885GF
XSON8
(SOT1089)
Reel 7” Q1/T1 or Q2/T3Active5874AUP1G885GF,115
( 9352 914 72115 )
74AUP1G885GN
XSON8
(SOT1116)
Reel 7” Q1/T1 or Q2/T3Active5874AUP1G885GN,115
( 9352 922 16115 )
74AUP1G885GS
XSON8
(SOT1203)
Reel 7” Q1/T1 or Q2/T3Active5874AUP1G885GS,115
( 9352 927 77115 )
74AUP1G885GT
XSON8
(SOT833-1)
Reel 7” Q1/T1 or Q2/T3ActivepS874AUP1G885GT,115
( 9352 807 67115 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期EFRIFRMTBF(小时)MSLMSL无铅
74AUP1G885DC74AUP1G885DC,12574AUP1G885DCAlways Pb-free33.011.07E911
74AUP1G885GF74AUP1G885GF,11574AUP1G885GFAlways Pb-free11
74AUP1G885GN74AUP1G885GN,11574AUP1G885GNAlways Pb-free33.011.07E911
74AUP1G885GS74AUP1G885GS,11574AUP1G885GSAlways Pb-free33.011.07E911
74AUP1G885GT74AUP1G885GT,11574AUP1G885GTAlways Pb-free33.011.07E911
品质及可靠性免责声明

文档 (11)

文件名称标题类型日期
74AUP1G885Low-power dual function gateData sheet2019-07-22
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g885aup1g885 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_document_Logic_CombinationLogic_infocard_201710Combination logic solutions cardLeaflet2017-10-16
Nexperia_Selection_guide_2022Nexperia Selection Guide 2022Selection guide2022-01-05
MAR_SOT1089MAR_SOT1089 TopmarkTop marking2013-06-03
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03

支持

在此页面中寻找您的设计问题答案。如有提供,您可以在我们的安世半导体支持社区找到相关信息,或者您可以找到安世半导体模型和设计工具。

模型

文件名称标题类型日期
aup1g885aup1g885 IBIS modelIBIS model2013-04-07

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品: https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号,我们的全球与区域经销网络可以协助您取得样品。