The HEF4020B-Q100 is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). Thecounteradvances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typ. 35 MHz at VDD = 15 V).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usuallyground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.