74AUP2G132GT

Low-power dual 2-input NAND Schmitt trigger

The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accepts standard input signals. They can transform slowly changing input signals into sharply defined, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

特性

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

目标应用

  • Wave and pulse shaper
  • Astable multivibrator
  • Monostable multivibrator

参数类型

型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP2G132GTProduction1.1 - 3.6CMOS+/- 1.910702ultra low-40~1253276.1157XSON8

Package

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74AUP2G132GT
XSON8
(SOT833-1)
SOT833-1Reel 7" Q1/T1ActiveaE274AUP2G132GT,115
( 9352 807 33115 )

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHF无铅转换日期EFRIFRMTBF(小时)MSLMSL无铅
74AUP2G132GT74AUP2G132GT,11574AUP2G132GTAlways Pb-free0.03.293.04E811
品质及可靠性免责声明

文档 (9)

文件名称标题类型日期
74AUP2G132low-power dual 2-input NAND Schmitt triggerData sheet2017-07-14
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN10343MicroPak soldering informationApplication note2010-12-30
AN11052Pin FMEA for AUP familyApplication note2011-05-06
AN10156Sorting through the low voltage logic mazeApplication note2013-03-13
75017458NXP ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logicBrochure2014-10-12
aup2g132aup2g132 IBIS modelIBIS model2013-04-08
SOT833-1_115Standard product orientation 12NC ending 115Packing2013-04-05
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyOutline drawing2018-10-18

支持

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模型

文件名称标题类型日期
aup2g132aup2g132 IBIS modelIBIS model2013-04-08

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