74HC4515; 74HCT4515

4-to-16 line decoder/demultiplexer with input latches; inverting

The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and 16 inverting outputs (Q0, to Q15).

When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input E does not affect the state of the latch. When the device is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs.

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

特性

Inverting outputs
CMOS input levels
16-line demultiplexing capability
Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs
Complies with JEDEC standard no. 7 A
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

目标应用

Digital multiplexing
Address decoding
Hexadecimal/BCD decoding

文档 (1)

文件名称	标题	类型	日期
74HC4515	4-to-16 line decoder, demultiplexer with input latches; inverting	Data sheet	2018-07-04

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