74AVC16374

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section.

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.

特性

Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standards:
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-1A (2.7 V to 3.6 V)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation
Low inductance multiple V_CC and GND pins to minimize noise and ground bounce
Supports Live Insertion

文档 (4)

文件名称	标题	类型	日期
74AVC16374	16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state	Data sheet	2017-05-03
AN90007	Pin FMEA for AVC family	Application note	2018-11-30
avc16374	74AVC16374 IBIS model	IBIS model	2019-01-09
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10

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模型

文件名称	标题	类型	日期
avc16374	74AVC16374 IBIS model	IBIS model	2019-01-09