74ALVC16835

18-bit registered driver; 3-state

The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).

When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF–state. Operation of the OE input does not affect the state of the latch/flip-flop.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性

Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
Input diodes to accommodate strong drivers
Complies with JEDEC standards:
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
- CDM JESD22-C101E exceeds 1000 V

文档 (2)

文件名称	标题	类型	日期
74ALVC16835A	18-bit registered driver; 3-state	Data sheet	2018-01-19
Nexperia_Selection_guide_2023	Nexperia Selection Guide 2023	Selection guide	2023-05-10

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