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74LVC1G57GW

Low-power configurable multiple function gate

The 74LVC1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Alternatives

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVC1G57GW 74LVC1G57GW,125 935276071125 SOT363-2 订单产品

特性

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8B/JESD36 (2.7 V to 3.6 V).

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.

参数类型

型号Product statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G57GWProductionn.a.n.a.TTL± 326.31501low-40~12527750.1165TSSOP6

PCB Symbol, Footprint and 3D Model

Model Name描述

Package

型号可订购的器件编号，（订购码(12NC)）状态标示封装尺寸版本回流焊/波峰焊包装
74LVC1G57GW74LVC1G57GW,125
( 9352 760 71125 ) 		ActiveYC
TSSOP6
(SOT363-2) 		SOT363-2SOT363-2_125

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符
74LVC1G57GW74LVC1G57GW,12574LVC1G57GW
品质及可靠性免责声明

系列

文档 (6)

文件名称标题类型日期
74LVC1G57Low-power configurable multiple function gateData sheet2023-08-18
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc1g5774LVC1G57 IBIS modelIBIS model2014-10-20
74LVC1G57GW_Nexperia_Product_Reliability74LVC1G57GW Nexperia Product ReliabilityQuality document2023-05-29
SOT363-2_125TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientationPacking information2022-11-04

支持

如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

模型

文件名称标题类型日期
lvc1g5774LVC1G57 IBIS modelIBIS model2014-10-20

PCB Symbol, Footprint and 3D Model

Model Name描述

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装Packing quantity在线购买
74LVC1G57GW74LVC1G57GW,125935276071125SOT363-2_125- 订单产品

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品： https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号，我们的全球与区域经销网络可以协助您取得样品。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册