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74LVC8T595

Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state

The 74LVC8T595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register.

VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins MR, SHCP, STCP, OE, DS and Q7S are referenced to VCC(A) and pins Qn are referenced to VCC(B).

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when VCC(A) is at GND level, the Qn outputs are in the high-impedance OFF-state.

特性

  • Wide supply voltage range:

    • VCC(A): 1.1 V to 5.5 V

    • VCC(B): 1.1 V to 5.5 V

  • High noise immunity

  • Suspend mode

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • ±24 mA output drive (VCC(A) = VCC(B) = 3.0 V)

  • Inputs accept voltages up to 5.5 V

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:

    • JESD8-12A (1.1 V to 1.3 V)

    • JESD8-11A (1.4 V to 1.6 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (3.0 V to 3.6 V)

    • JESD12-6 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC8T595BQProduction1.1 - 5.51.1 - 5.5CMOS/LVTTL± 244.18low-40~125767.347DHVQFN20
74LVC8T595PWProduction1.1 - 5.51.1 - 5.5CMOS/LVTTL± 244.18low-40~1251004.343TSSOP20

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC8T595BQ
DHVQFN20
(SOT764-1) 		SOT764-1SOT764-1_115ActiveLVC8T59574LVC8T595BQX
( 9353 091 43115 )
74LVC8T595PW
TSSOP20
(SOT360-1) 		SOT360-1SSOP-TSSOP-VSO-WAVE
SOT360-1_118ActiveVC8T59574LVC8T595PWJ
( 9353 091 44118 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC8T595BQ74LVC8T595BQX74LVC8T595BQweek 25, 2019
74LVC8T595PW74LVC8T595PWJ74LVC8T595PWweek 25, 2019
品质及可靠性免责声明

文档 (7)

文件名称标题类型日期
74LVC8T595Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-stateData sheet2023-08-29
Nexperia_document_guide_Logic_translatorsNexperia Logic TranslatorsBrochure2021-04-12
Nexperia_document_leaflet_Logic_74LVC8T595_201711Voltage-translating Shift Register for Modular DesignsLeaflet2017-11-29
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT764-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm bodyPackage information2022-06-21
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT360-1plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm bodyPackage information2022-06-21

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