The 74HC161-Q100 is a synchronous preset table binary counter with an internal look-head carry.
Synchronous operation is provided by having all flip-flops clocked simultaneously on the
positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be
preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3)
to be loaded into the counter on the positive-going edge of the clock. Preset takes
place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master
reset input (MR) sets Q0 to Q3 LOW regardless of the
levels at input pins CP, PE, CET and CEP (thus providing
an asynchronous clear function). The look-ahead carry simplifies serial cascading of the
counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used
to enable the next cascaded stage. The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP to CP set-up time, according to
the following formula:
f(max) = 1 /( t P(max) (CPtoTC) + t SU (CEPtoCP) ).
Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.