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74AUP1G74

Low-power D-type flip-flop with set and reset; positive-edge trigger

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 0.8 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Overvoltage tolerant inputs to 3.6 V

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G74DCProduction0.8 - 3.6CMOS± 1.99.2400ultra low-40~12520334.1113VSSOP8
74AUP1G74GNProduction0.8 - 3.6CMOS± 1.99.2400ultra low-40~12523810.6148XSON8
74AUP1G74GSProduction0.8 - 3.6CMOS± 1.99.2400ultra low-40~12527610.8146XSON8
74AUP1G74GTProduction0.8 - 3.6CMOS± 1.99.2400ultra low-40~1253276.1157XSON8
74AUP1G74GXProduction0.8 - 3.6CMOS± 1.99.2400ultra low-40~1252566.5148X2SON8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AUP1G74DC
VSSOP8
(SOT765-1) 		SOT765-1SOT765-1_125Activep7474AUP1G74DC,125
( 9352 807 17125 )
74AUP1G74GN
XSON8
(SOT1116) 		SOT1116REFLOW_BG-BD-1
SOT1116_115Active5474AUP1G74GN,115
( 9352 922 15115 )
74AUP1G74GS
XSON8
(SOT1203) 		SOT1203REFLOW_BG-BD-1
SOT1203_115Active5474AUP1G74GS,115
( 9352 927 75115 )
74AUP1G74GT
XSON8
(SOT833-1) 		SOT833-1SOT833-1_115Activep7474AUP1G74GT,115
( 9352 807 18115 )
74AUP1G74GX
X2SON8
(SOT1233-2) 		SOT1233-2SOT1233-2_115Active5474AUP1G74GXX
( 9353 084 41115 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AUP1G74DC74AUP1G74DC,12574AUP1G74DCAlways Pb-free
74AUP1G74GN74AUP1G74GN,11574AUP1G74GNAlways Pb-free
74AUP1G74GS74AUP1G74GS,11574AUP1G74GSAlways Pb-free
74AUP1G74GT74AUP1G74GT,11574AUP1G74GTAlways Pb-free
74AUP1G74GX74AUP1G74GXX74AUP1G74GXweek 25, 2019
品质及可靠性免责声明

文档 (17)

文件名称标题类型日期
74AUP1G74Low-power D-type flip-flop with set and reset; positive-edge triggerData sheet2023-07-14
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g74aup1g74 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT1233-2plastic thermal enhanced extremely thin small outline package; no leads;8 terminals; body 1.35 x 0.8 x 0.32 mmPackage information2022-04-21
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2022-06-03
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2022-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2022-06-02
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06

支持

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模型

文件名称标题类型日期
aup1g74aup1g74 IBIS modelIBIS model2013-04-07

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