特性
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- Ideal for addressable register applications
- Data enable for address and data synchronization
- Eight positive-edge triggered D-type flip-flops
- Input levels:
- For 74AHC377: CMOS level
- For 74AHCT377: TTL level
- ESD protection:
- HBM EIA/JESD22-A114E exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- CDM EIA/JESD22-C101C exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
文档 (3)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74AHC_AHCT377 | Octal D-type flip-flop with data enable; positive-edge trigger | Data sheet | 2017-07-20 |
ahc377 | ahc377 IBIS model | IBIS model | 2013-04-07 |
ahct377 | ahct377 IBIS model | IBIS model | 2013-04-07 |