Nexperia
Or cross multiple parts
×

74AUP1T98-Q100

Low-power configurable gate with voltage-level translator

The 74AUP1T98-Q100 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications.

This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 2.3 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Complies with JEDEC standards

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • Low static power consumption; ICC = 1.5 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1T98GW-Q100Production2.3 - 3.6CMOS± 1.98.7701ultra low-40~12526438.6153TSSOP6

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AUP1T98GW-Q100
TSSOP6
(SOT363-2) 		SOT363-2SOT363-2_125ActiveaR74AUP1T98GW-Q100H
( 9353 039 92125 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AUP1T98GW-Q10074AUP1T98GW-Q100H74AUP1T98GW-Q100Always Pb-free
品质及可靠性免责声明

文档 (6)

文件名称标题类型日期
74AUP1T98_Q100Low-power configurable gate with voltage-level translatorData sheet2023-07-17
AN10161PicoGate Logic footprintsApplication note2002-10-29
aup1t98aup1t98 IBIS modelIBIS model2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT363-2plastic thin shrink small outline package; 6 leads; body width 1.25 mmPackage information2022-11-21

支持

如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

模型

文件名称标题类型日期
aup1t98aup1t98 IBIS modelIBIS model2014-12-21

订购、定价与供货

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品： https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号，我们的全球与区域经销网络可以协助您取得样品。