16-bit dual supply translating transceiver; 3-state

The 74ALVC164245-Q100 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The 74ALVC164245-Q100 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.

This device can be used as two 8-bit transceivers or one 16-bit transceiver.

The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).

In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode).

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.


  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range:
    • 3 V port (VCC(A)): 1.5 V to 3.6 V
    • 5 V port (VCC(B)): 1.5 V to 5.5 V
  • CMOS low power consumption
  • Overvoltage tolerant inputs to 5.5 V
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Control inputs voltage range from 2.7 V to 5.5 V
  • High-impedance outputs when VCC(A) or VCC(B) = 0 V
  • Complies with JEDEC standards:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)


Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74ALVC164245DGG-Q100Production1.5 - 5.51.5 - 3.6CMOS/LVTTL± 242.916low-40~85822.037TSSOP48


Reel 13" Q1/T1ActiveALVC16424574ALVC164245DGG-QJ
( 9353 007 61118 )


型号可订购的器件编号化学成分RoHS / RHF无铅转换日期EFRIFRMTBF(小时)MSLMSL无铅
74ALVC164245DGG-Q10074ALVC164245DGG-QJ74ALVC164245DGG-Q100Always Pb-free19.30.52E911

文档 (3)

74ALVC164245_Q10016-bit dual supply translating transceiver; 3-stateData sheet2021-07-27
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT362-1plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm bodyPackage information2020-04-21


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