The NCA9534 is an 8-bit bidirectional I/O expander compliant with I²C and SMBus protocols, operating over a wide supply range of 1.65 V to 5.5 V. It enables remote GPIO expansion for microcontroller-based systems via a standard two⁠-⁠wire interface (SCL/SDA), supporting clock frequencies up to 1 MHz (Fast-Mode Plus). Key performance features include high output drive capability, 5 V-tolerant I/O pins for mixed-voltage interfacing, reduced supply current, individual I/O direction configuration and compact TSSOP16 package.

I/O expanders such as the NCA9534 provide an efficient, low-overhead solution for extending microcontroller GPIO resources in applications requiring additional digital interfaces, including user interface (LEDs, push-buttons, switches), sensing and monitoring (sensor inputs, peripheral status), power and control (relays, fan control and peripheral enable/ disable), industrial automation (PLC expansion, motor drivers), automotive systems (ECU controls, dashboard indicators), consumer electronics (wearables, remotes and tablets) and medical devices (monitoring interface, alarms).

The NCA9534 device incorporates four 8-bit registers accessible via the I²C/SMBus interface: Configuration register (defines each I/O pin as input or output), Input Port register (reflects the real-time logic state of the I/O pins when configured as inputs), Output Port register (stores the drive state for pins configured as outputs in push-pull operation), and Polarity Inversion register (enables optional logic inversion of the Input Port register values for active-high or active-low operation).

The system controller configures I/O direction by writing to the Configuration register. Input data is latched into the Input Port register and may be read at any time. Output data is driven according to the contents of the Output Port register. Polarity inversion, when enabled, inverts the logical sense of the Input Port register without affecting the physical pin state.

An active-low, open-drain interrupt (INT) output asserts when any input pin differs from its corresponding bit in the Input Port register. This change-on-state detection minimizes host polling and supports event-driven system architecture. The INT signal is de-asserted upon a read of the Input Port register that captures the current pin states. Integrated power on reset (POR circuitry initializes all registers to their default states and resets the internal state machine), resetting the IC through dynamic power sequencing in case of bus stuck. Three hardware address pins (A0, A1, A2) allow the configuration of up to eight NCA9534 devices to coexist on the same I²C/SMBus segment without address conflicts.