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74AUP1G11GN ECAD models PCB Symbol, Footprint & ECAD Model

Low-power 3-input AND gate

The 74AUP1G11 provides a low-power, low-voltage single 3-input AND gate.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74AUP1G11GN 74AUP1G11GN,132 935291721132 SOT1115 订单产品

特性

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 µA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

目标应用

参数类型

型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP1G11GNProduction1.1 - 3.6CMOS± 1.96.9701ultra low-40~12527511.7171XSON6

Package

型号可订购的器件编号,(订购码(12NC))状态标示封装尺寸版本回流焊/波峰焊包装
74AUP1G11GN74AUP1G11GN,132
( 9352 917 21132 )
ActivepU
XSON6
(SOT1115)
SOT1115Reel 7" Q1/T1, Q3/T4

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHFMSLMSL无铅
74AUP1G11GN74AUP1G11GN,13274AUP1G11GN11
品质及可靠性免责声明

文档 (6)

文件名称标题类型日期
74AUP1G11Low-power 3-input AND gateData sheet2018-08-20
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup1g11aup1g11 IBIS modelIBIS model2014-12-21
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
SOT1115_132Reversed product orientation 12NC ending 132Packing2013-04-04
SOT1115plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm bodyOutline drawing2018-11-14

支持

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模型

文件名称标题类型日期
aup1g11aup1g11 IBIS modelIBIS model2014-12-21

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装在线购买
74AUP1G11GN74AUP1G11GN,132935291721132Reel 7" Q1/T1, Q3/T4订单产品

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品: https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

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