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74LVC163PW ECAD models PCB Symbol, Footprint & ECAD Model

Presettable synchronous 4-bit binary counter; synchronous reset

The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula: fmax=1/(tPHL(max)+tsu)


型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVC163PW 74LVC163PW,118 935210560118 SOT403-1 订单产品
74LVC163PW 74LVC163PW,112 935210560112 SOT403-1 订单产品


  • Wide supply voltage range from 1.2 V to 3.6 V
  • Inputs accept voltages up to 5.5 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Synchronous reset
  • Synchronous counting and loading
  • Two count enable inputs for n-bit cascading
  • Positive edge-triggered clock
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-B exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C



型号Product statusVCC (V)Output drive capability (mA)Logic switching levelstpd (ns)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC163PWProduction1.2 - 3.6± 24CMOS/LVTTL4.9low-40~1251254.654.7TSSOP16


( 9352 105 60118 )
Reel 13" Q1/T1
( 9352 105 60112 )
ActiveLVC163Bulk Pack


型号可订购的器件编号化学成分RoHS / RHFEFRIFRMTBF(小时)MSLMSL无铅

文档 (7)

74LVC163Presettable synchronous 4-bit binary counter; synchronous resetData sheet2017-05-03
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc163lvc163 IBIS modelIBIS model2013-04-07
lvclvc Spice modelSPICE model2013-05-06
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT403-1_118TSSOP16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-08
SOT403-1plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.1 mm bodyOutline drawing2018-11-14


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lvc163lvc163 IBIS modelIBIS model2013-04-07
lvclvc Spice modelSPICE model2013-05-06


型号Orderable part numberOrdering code (12NC)包装在线购买
74LVC163PW74LVC163PW,118935210560118Reel 13" Q1/T1订单产品
74LVC163PW74LVC163PW,112935210560112Bulk Pack订单产品