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74ALVCH16823DGG ECAD models PCB Symbol, Footprint & ECAD Model

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section.

With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock.

When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74ALVCH16823DGG 74ALVCH16823DGGS 935259030512 SOT364-1 订单产品
74ALVCH16823DGG 74ALVCH16823DGGY 935259030518 SOT364-1 订单产品
74ALVCH16823DGG 74ALVCH16823DGG:11 935259030112 SOT364-1 订单产品
74ALVCH16823DGG 74ALVCH16823DGG,11 935259030118 SOT364-1 订单产品

特性

  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low-power consumption
  • Direct interface with TTL levels
  • Current drive ± 24 mA at 3.0 V
  • MULTIBYTE flow-through standard pin-out architecture
  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce
  • Output drive capability 50 Ω transmission lines at 85°C
  • All data inputs have bushold
  • Complies with JEDEC standard no. 8-1A
  • Complies with JEDEC standards:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    • CDM JESD22-C101E exceeds 1000 V

目标应用

参数类型

型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVCH16823DGGProduction1.2 - 3.6TTL± 242.1350low-40~859321.0TSSOP56

Package

型号可订购的器件编号,(订购码(12NC))状态标示封装尺寸版本回流焊/波峰焊包装
74ALVCH16823DGG74ALVCH16823DGGS
( 9352 590 30512 )
ActiveALVCH16823
TSSOP56
(SOT364-1)
SOT364-1SSOP-TSSOP-VSO-WAVE
Tube in Drypack
74ALVCH16823DGGY
( 9352 590 30518 )
ActiveALVCH16823Reel 13" Q1/T1 in Drypack

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHFEFRIFRMTBF(小时)MSLMSL无铅
74ALVCH16823DGG74ALVCH16823DGGS74ALVCH16823DGG123.83.872.58E822
74ALVCH16823DGG74ALVCH16823DGGY74ALVCH16823DGG123.83.872.58E822
品质及可靠性免责声明

文档 (5)

文件名称标题类型日期
74ALVCH1682318-bit bus-interface D-type flip-flop with reset and enable; 3-stateData sheet2018-02-02
alvch16823alvch16823 IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT364-1_118TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-15
SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyOutline drawing2018-10-18

支持

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模型

文件名称标题类型日期
alvch16823alvch16823 IBIS modelIBIS model2013-04-07

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装在线购买
74ALVCH16823DGG74ALVCH16823DGGS935259030512Tube in Drypack订单产品
74ALVCH16823DGG74ALVCH16823DGGY935259030518Reel 13" Q1/T1 in Drypack订单产品
74ALVCH16823DGG74ALVCH16823DGG:11935259030112Bulk Pack订单产品
74ALVCH16823DGG74ALVCH16823DGG,11935259030118Reel 13" Q1/T1订单产品

样品

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