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74LVC16373ADL NRND ECAD models PCB Symbol, Footprint & ECAD Model

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.

The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

不建议用在新设计中(NRND),替代产品使用单击此处

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVC16373ADL 74LVC16373ADL,118 935235160118 SOT370-1 订单产品
74LVC16373ADL 74LVC16373ADL,112 935235160112 SOT370-1 订单产品

特性

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Multibyte flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16373A only)
  • High-impedance when VCC = 0 V
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-B exceeds 200 V
    • CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

目标应用

参数类型

型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74LVC16373ADL
NRND
Not for design in1.2 - 3.6TTL+/- 24316low-40~1258825.0SSOP48

Package

型号可订购的器件编号,(订购码(12NC))状态标示封装尺寸版本回流焊/波峰焊包装
74LVC16373ADL
NRND
74LVC16373ADL,118
( 9352 351 60118 )
ActiveLVC16373A
SSOP48
(SOT370-1)
SOT370-1SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1
74LVC16373ADL,112
( 9352 351 60112 )
ActiveLVC16373ABulk Pack

品质、可靠性及化学成分

型号可订购的器件编号化学成分RoHS / RHFMSLMSL无铅
74LVC16373ADL
NRND
74LVC16373ADL,11874LVC16373ADL11
74LVC16373ADL
NRND
74LVC16373ADL,11274LVC16373ADL11
品质及可靠性免责声明

文档 (7)

文件名称标题类型日期
74LVC_LVCH16373A16-bit D-type transparant latch with 5 V tolerant inputs/outputs; 3-stateData sheet2019-02-15
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc16373alvc16373a IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SSOP-TSSOP-VSO-REFLOWFootprint for reflow solderingReflow soldering2009-10-08
SOT370-1_118Standard product orientation 12NC ending 118Packing2013-04-19
SOT370-1plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm bodyOutline drawing2018-10-18

支持

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模型

文件名称标题类型日期
lvc16373alvc16373a IBIS modelIBIS model2013-04-07

订购、定价与供货

型号Orderable part numberOrdering code (12NC)包装在线购买
74LVC16373ADL74LVC16373ADL,118935235160118Reel 13" Q1/T1订单产品
74LVC16373ADL74LVC16373ADL,112935235160112Bulk Pack订单产品

样品

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