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74LVCH162373ADGG ECAD models PCB Symbol, Footprint & ECAD Model

16-bit D-type transparent latch

The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state outputs for bus-oriented applications. One latch enable (pin nLE) input and one output enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition, the latches are transparent, that is, the latch output changes each time its corresponding data inputs changes. When pin nLE is LOW, the latches store the information that was present at the data inputs a set-up time preceding the HIGH to LOW transition of pin nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.

The device is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to reduce line noise. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.


型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVCH162373ADGG 74LVCH162373ADGG,1 935238750112 SOT362-1 订单产品
74LVCH162373ADGG 74LVCH162373ADGG:1 935238750118 SOT362-1 订单产品
74LVCH162373ADGG 74LVCH162373ADGG,5 935238750512 SOT362-1 订单产品
74LVCH162373ADGG 74LVCH162373ADGG:5 935238750518 SOT362-1 订单产品


  • 5 V tolerant inputs/outputs for interfacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Multibyte flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bushold (74LVCH162373A only)
  • High-impedance when VCC = 0 V
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-B exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C



型号Product statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVCH162373ADGGProduction1.2 - 3.6TTL± 243.216low-40~125822.037TSSOP48


( 9352 387 50112 )
Bulk Pack
( 9352 387 50118 )
ActiveLVCH162373AReel 13" Q1/T1


型号可订购的器件编号化学成分RoHS / RHFEFRIFRMTBF(小时)MSLMSL无铅

文档 (6)

74LVC_LVCH162373A16-bit D-type transparant latch; 30 Ohm series termination resistors; 5 V tolerant inputs/outputs; 3-stateData sheet2017-05-03
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvch162373alvch162373a IBIS modelIBIS model2013-04-07
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT362-1_118TSSOP48; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code (12NC) ending 118Packing2013-04-15
SOT362-1plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm bodyOutline drawing2018-10-18


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lvch162373alvch162373a IBIS modelIBIS model2013-04-07


型号Orderable part numberOrdering code (12NC)包装在线购买
74LVCH162373ADGG74LVCH162373ADGG,1935238750112Bulk Pack订单产品
74LVCH162373ADGG74LVCH162373ADGG:1935238750118Reel 13" Q1/T1订单产品
74LVCH162373ADGG74LVCH162373ADGG,5935238750512Tube in Drypack订单产品
74LVCH162373ADGG74LVCH162373ADGG:5935238750518Reel 13" Q1/T1 in Drypack订单产品